EEPROM cells are nonvolatile memory cells that may be electrically programmed, read, and erased. EEPROM cells typically include two transistors referred to as a floating gate transistor and a select or isolation transistor. The select transistor is typically used to select the floating gate transistor for reading or programming. The floating gate transistor may be programmed using Fowler-Nordheim tunneling to store either a positive or negative charge on its floating gate.
A cross-section of a typical conventional EEPROM cell 100 is shown in FIG. 1A. EEPROM cell 100 is formed on semiconductor substrate 102 and includes a select transistor 124 and a floating gate transistor 122. Select transistor 124 includes source region 106, drain region 108, gate oxide 112 and select gate 116. Floating gate transistor 122 includes source region 104, drain region 106 (which it shares with select gate 106), tunnel oxide 110, floating gate 118, interlayer dielectric 114, and control gate 120. Erasing of floating gate transistor 122 is typically accomplished by storing negative charge on floating gate 118. This may be accomplished by applying a large positive voltage to control gate 120 and grounding regions 104 and 106 such that electrons may tunnel through tunnel oxide 110 to floating gate 118. Programming of floating gate transistor 122 may be accomplished by applying a large positive voltage to select gate 116 (e.g., 15-20 volts), applying a large positive voltage to drain region 108, applying ground to control gate 120, and floating source region 104. In this configuration, electrons may tunnel from floating gate 118 to region 106 through tunnel dielectric 118 to create a positive charge on floating gate 118.
One disadvantage of EEPROM cell 100 is that it generally requires the formation of two different oxide thicknesses. Tunnel oxide 110 generally needs to be thin enough to enable electron tunneling (e.g., less than 125 angstroms). Gate oxide 112 is generally significantly thicker (e.g., 200 to 500 angstroms) than tunnel oxide 110 as gate oxide 112 must be able to withstand the high positive program voltages supplied to select gate 116 without breaking down. Forming two different oxide thicknesses generally increases the complexity and cost of forming EEPROM cell 100. U.S. Pat. No. 5,471,422 discloses an EEPROM cell that uses only tunnel oxide 110 in the formation of its floating gate and select gate transistors.
Another disadvantage of EEPROM cell 100 is that the size is generally large due to the high positive voltage applied to select gate 116 for programming. The high positive voltage typically requires that the channel region of select transistor 124 (i.e., between regions 106 and 108) be increased to avoid punch-through of the region. This generally negatively impacts the speed of EEPROM cell 100. The cell size may also be generally large due to the formation of control gate 120 over floating gate 118. Control gate 120 is typically formed over floating gate 118 after regions 104 and 106 are formed. Thus, lateral diffusion of regions 104 and 106 that occurs when forming layer 114 or control gate 120 may be significant and may lead to punch-through problems. The channel region between regions 104 and 106 is typically increased to reduce the likelihood of punch-through problems. Control gate 120 is also typically formed to overlap each side of floating gate 118 by a certain amount to account for alignment tolerances between layers. Due to minimum spacing requirements between features in a particular process, this also generally increases the size of EEPROM cell 100.
FIG. 1B shows EEPROM cell 100 formed in another conventional manner with tunnel oxide 110 forming a tunnel window 111 over region 106. The cell size is generally increased in FIG. 1B by forming tunnel window 111 over region 106. This is generally due to allowance of processing and lithographic alignment tolerances in forming tunnel window 111 after region 106 which tends to increase the length of region 106. Additionally, select transistor 124 typically requires additional graded source and drain junctions so as to pass high voltages, and long effective channel lengths to prevent drain to source punch through when select transistor 124 is off. This tends to increase the processing complexity and size of cell 100. A top view of FIG. 1B is shown in FIG. 1C.
FIG. 2 shows a conventional EEPROM array 200 and decoder circuitry. EEPROM array 200 includes EEPROM cells 100 and 202 each having a select gate and a floating gate as illustrated in FIG. 1. Each EEPROM cell is connected to decoder circuitry for providing the appropriate voltages for programming, erasing, or reading the cells. During programming, reading, or erasing, generally one row of EEPROM cells is selected and all other rows are deselected. Row decoders 204 and 210 may decode an address and determine which of EEPROM cells 100 or 202 may be selected for a designated operation. High voltage decoders 206 and 212 may then apply the appropriate program voltage (VPP), erase voltage (VE), or read voltage (VR) to the gates of the select transistors, and high voltage decoders 208 and 214 may apply the appropriate program voltage (VFP), erase voltage (VFE), or read voltage (VFR) to the floating gate transistors of EEPROM cells 100 and 202. The design an implementation of the decoder circuitry can be complex as voltages for the selected and deselected cells are different at the same time. Additionally, the decoder may have to simultaneously generate both positive voltages and negative voltages at the same time.
Therefore, what is needed is an EEPROM cell that is compact, can be manufactured without significant process complexity, and that may be programmed, erased, and read using less complex decoder circuitry.